1. Field of the Invention
The present invention relates generally to partial response maximum likelihood (PRML) detection of coded signals using the Viterbi algorithm. The present invention is particularly useful for recovering precoded signals recorded on a high-density storage medium or transmitted on a communication link
2. Description of the Related Art
Partial response maximum likelihood detection technique is currently receiving attentions due to its powerful error correcting capability on high density signals. A number of different high-density coding methods such as (1, 7) run-length limited coding and EFM (eight-to-fourteen modulation) coding have been developed and Viterbi algorithm is used for maximum likelihood sequence detection. However, different coding schemes are currently employed for optical discs although their size and appearance are substantially the same. Since the Viterbi decoder must be designed to specifically meet the coding method employed, more than one Viterbi decoder would be required if optical discs of different coding format were to be used on a single playback system.
More specifically, for processing coded signals with no run length constraint, PRML detection would require a branch metric calculator, ACS (add/compare/select) circuitry and a path memory having a series of many memory stages. The ACS circuit includes two ACS sub-circuits each comprising a pair of adders, a comparator and a selector. A set of branch metrics (x.sub.i .+-.1).sup.2 and x.sub.1.sup.2 is produced from an input bit sequence and applied to the adders of each ACS sub-circuit where one of the branch metrics of each ACS sub-circuit are summed with a previous path metric of the other ACS sub-circuit, while the other branch metric of each ACS sub-circuit is summed with a previous path metric of its own ACS sub-circuit. In each ACS sub-circuit, the outputs of the adders are compared with each other and a smaller of the two is determined by the comparator and selected. Each memory stage of the path memory includes two unit delay elements. The outputs of the comparators of both ACS sub-circuits are used as path select signals In each memory stage for determining a maximum likelihood bit sequence that appears on a surviving path of the trellis diagram.
On the other hand, if the (1, 7) run-length limited coding is used, two adders would be additionally provided in the ACS circuitry. Each additional adder produces a path metric by summing the branch metric x.sub.i.sup.2 with a previous path metric received from one of the ACS sub-circuits and supplying its output to the other ACS sub-circuit. Each memory stage of the path memory for the (1, 7) run-length limited coding would include additional two unit memories. Thus, a significant amount of hardware would be required if different channel codes were to be processed individually by different PRML decoders.